Custom Layout

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Custom Layout

Why CL?

Layout Engineers are responsible for developing the Layouts from scratch.IP's like Std Cells, Memories(SRAM&ROM) and AMS Blocks (PLL, ADC, DAC & Amplifiers) are full custom designed&it requires special skills to develop the quality layouts.

Course overview - CL

  •  16 weeks program
  •  8 hour classroom session
  •  Program covers modules from basic electronics to Layout design
  •  Course completion Certificate after successful completion of the program


Course overview - CL

Trainer – CL

Have 15+ years of experience in Semiconductor industry

Trainer have strong expertise on Analog & Mixed Signal Layout, SERDES, GPIO & High speed IOs

Have worked on Technologies like 10nm, 14nm, 16nm (FinFET), 20nm, 28nm, 45nm, 65nm, 90nm, 130nm, 180nm & 350nm

Worked with various foundries like Renesas , TSMC, Intel, TI, IBM, DongBu-HiTek, Micrel etc.

Experienced in SERDES blocks like Rx_top, Bias_top, VGA, DFE, CDR, Refgen, Lane_top.

Experienced in handling Analog blocks like BGR, LDO, PLL, Oscillator, Op-Amp, POR etc.

Have worked on High-speed IO blocks.

Developed and Verified the IO Libraries (Generic and CUP IOs) around 10 tap outs.

Have good knowledge on DSM, Double patterning and G rules, LEF creations & RC extractions

Trainer 1

Syllabus – CL

  •  Module 1: Basic curriculum
    •  Digital: Logic gates, Boolean algebra, Latches, Flip-flops etc.
    •  Analog: Op-Amp
    •  Computing: Unix commands and their usage, gvim & VI editor
  •  Module 2: Basic Electronics
    •  Concepts of voltage, current, power and energy.
    •  R, L & C) Resistance, Inductance and Capacitance components and their effects in Layout
    •  Introduction to VLSI, PN junction, CMOS, BJT, etc.
  •  Module 3: CMOS Overview
    •  Basics of CMOS operation, fabrication & characteristics
    •  CMOS technology, Second order effects,
    •  FinFET Technology and challenges
  •  Module 4: Circuit Designs
    •  Digital: NAND, NOR, Latch, FF etc.
    •  Analog: Current mirror, Diff pairs, amplifiers, regulators etc.
  •  Module 5: Layout Designs
    •  Introduction Layout tools, Layers
    •  Layout designs of Standard cells & Analog blocks.
    •  Verification: LVS,DRC, ERC, Parasitic extraction.
    •  Fingers, multiplier, tap, Guarding, bulk connections.
  •  Module 6: Advanced topics
    •  Cross-talk, SI
    •  EM & IR.
    •  Matching.
    •  Antenna effect, STI, LOD, WPE, ESD etc.
  •  Module 7: Projects as per Industry standards
    •  BGR, LDO, Opamp : Layout from scratch.
    •  Layout consideration, Floor plan, placement, Power planning, routing, Matching
    •  Verification, Layout optimization
    •  IP Finishing technique.

Labs - CL

  •  Labs are done using most prominent and widely used tools in the industry
  •  Real time hands – on projects

Who can attend - CL

Engineering Graduates (BTech, BE, BS)

Engineering Post-Graduates (MTech, ME, MS)

Experienced Engineers who want to change their domain to Design Verification

Experienced Engineers who want to improve their Design Verification skills

College faculties who want to gain Industry knowledg