Physical Design

Why PD?

Physical Design is conversion of a set of gates connected through nets (netlist) to a layout form in a given chip area meeting aspects of power, area, performance (STA) honouring time to market. Floorplan, placement of cells, clock building, routing of metals connecting the logic gates and meeting the desired timing frequency is the goal of Physical Design.

Course overview - PD (Level-1)

	12 weeks program
	Program covers all aspects of Netlist to GDSII flow (refer syllabus for Level-1)
	Every topic and sub-topic covers industry oriented practical aspects
	Every topic and sub-topic is taught with hands-on lab from NL to GDSII
	Coverage of topics like Advanced Digital Design, CMOS, PnR flow, Sign-Off STA, Physical Verification, TCL are key differentiators in the program
	This program is primer program for entrants to VLSI industry
	Curriculum and projects are co-developed with inputs from Industry experts
	Soft skill training on the fly during the sessions
	Resume preparation guidance
	Regular assessment of areas where program members need improvement within scope of Level-1 program
	In depth learning by interlinked theory and labs in parallel for NL2GDSII flow
	Course completion certificate after completion of the program
	Trainers and Mentors available anytime for discussion
	Initial step to enter VLSI industry will be clear once this program is completed
	Labs can be accessed 24x7 through VPN from anywhere

Trainer

	Comes with 20+ years of industry experience.
	Comes with 15+ years of training experience.
	Successfully taped out 50+ designs.
	Executed Full Chip, Sub-System and block levels creating partitions.
	Have worked on Signoff like STA, Full-CHIP PV & IR etc.
	Trained about 1000+ engineers worldwide.
	Trainer has experience in leading a team of 60+ engineers.
	Working on Full Chip and methodology development.
	Technology node expertise from 5nm till 250nm across various foundries.
	Strong hands on experience in Synopsys and Cadence tool sets.
	Strong in TCL and PERL Scripting.

Syllabus - PD (Level-1)

Basic:

Module 1: Digital Circuit Design
Module 2: CMOS Circuit & Layout Design
Module 3: Linux Operating System
Module 4: ASIC/SOC Design flow
Module 5: PDK and Technology Library
Module 6: Standard Cell & Macro Libraries
Module 7: Timing Constraint ( SDC ) Development
Module 8: Static Timing Analysis

Implementation:

Module 9: Introduction to Physical Design Flow
Module 10: Design Planning (Floorplan)
Module 11: Power-Routing
Module 12: Physical Cells Placement & Std-Cell Pre-Placement
Module 13: Std-Cell Placement
Module 14: Scan-Chain Re-Ordering
Module 15: Pre-CTS Timing Analysis & Optimization
Module 16: CTS
Module 17: Post-CTS Timing Analysis & Optimization
Module 18: Routing

Signoff Checks:

Module 19: Physical Verification
Module 20: RC Extraction
Module 21: Sign-off STA Checks
Module 22: Timing Closure
Module 23: ECO Implementation
Module 24: Logical Equivalence Check
Module 25: IR-Drop and Electromigration Analysis Flow

Advanced Topics:

Module 26: Make-Flow & LSF

Projects:

Module 27: Final Project ( One Design )

	Semiconductor industry veteran with about 20 years and expert in the areas of RTL Coding, Physical Design and STA
	Immense knowledge in algorithmic level of implementation tools like Synopsys, Cadence etc
	Have held multiple positions like Product Engineering, Design and Application Engineering and driven start-ups
	Experienced in block level, sub-system level and Full Chip level Synthesis, PD and STA closures
	Have worked for companies like Cadence, Magma, Synopsys, Infineon, Mediatek, Qualcomm, Intel across geographies
	500+ Engineers have been trained across the globe

	#3, 3rd Cross, 6th Main, Vinayaka Layout, Marathahalli, Bangalore-560 037, Karnataka
	+91 80726 65956
	training@vlsimentors.com