Design verification is combination of both digital design and advanced verification technologies. It's a combination of HDL and HVL for RTL design and performs verification using advanced technologies like UVM & Python based scripts.
16 weeks program |
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Program covers all the aspects of Gate-Level to Netlist |
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Covers modules like Advanced Digital Design, Advanced Verilog coding, FSM modules, Memories, OOPS, System-Verilog concepts, Randomizations, Assertions, Test-bench environment creations and Scripting |
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Course module is framed by Semiconductor industry veterans |
Trainer has 10+ years of vast experience in both industry and academia |
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Strong Hands-on experience in the area of digital design, RTL coding, FPGA/ASIC architecture definitions, Algorithmic level implementation in Altera (Intel) & Xilinx FPGAs |
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Have held various positions in industry like Design verification engineer & FPGA design engineer |
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Worked in ISRO as a Research Assistant in the CHIP Design Group |
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Trained 300+ fresh graduates & engineering professionals across the globe |
Module 1: Introduction about VLSI technology |
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Module 2: Digital design |
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Module 3: Advanced Digital design |
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Module 4: Introduction to Verilog-HDL |
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Module 5: Verilog HDL program construct |
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Module 6: Task & function, Modeling Techniques, Timing control, Timing checks |
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Module 7: Data types, Arrays, Queue, Structure, Unions |
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Module 8: System Verilog, Mailbox & Packages, Randomization & constraints |
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Module 9: Assertion basics |
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Module 10: UVM introduction, Factory overrides, UVM reporting |
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Module 11: TLM |
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Module 12: UVM diver, sequencer, monitor, agent, environment |
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Module 13: Register Abstraction Layer (RAL) |
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Module 14: Functional Coverage model & Subscriber |
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Module 15: Reference model |
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Module 16: Real time projects with advanced protocols to build candidates professional expertise |
Engineering Graduates (BTech, BE, BS) |
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Engineering Post-Graduates (MTech, ME, MS) |
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Experienced Engineers who want to change their domain to Design Verification |
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Experienced Engineers who want to improve their Design Verification skills |
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College faculties who want to gain Industry knowledge |
