- Setup time equation ?
- Hold time equation ?
- Differences between flop and a latch ?
- What are different ways to fix a setup time violation ?
- What are different ways to fix a hold time violation ?
- What is GBA analysis ?
- What is PBA analysis?
- What is the difference between GBA and PBA analysis ?
- What is AOCV ?
- What is POCV ?
- Explain the concept of statistical OCV?
- What is a ring oscillator, how do you determine the frequency of a ring oscillator ?
- What is CRPR ?
- Single cycle path, multicycle path, false path, zero cycle path differences ? Write the constraints for a multicycle path of 3 and zero cycle path?
- Setup and hold constraint equations for multicycle path, zero cycle path ?
- Explain IO budgeting?
- What is Antenna effect?
- What is crosstalk ?
- Different methods to minimize clock crosstalk ? Should we fix data crosstalk?
- How does crosstalk affect setup timing and hold timing ?
- Which cells among HVT, SVT, LVT cells have more variation w.r.t. P, V, T ?
- What is a lockup latch, explain its applications ? Why should we add a lockup latch?
- How many timing corners you sign-off your chip ?
- How to design and write Verilog code for asynchronous FIFO? Why do we need a FIFO
- What are the differences between SRAM and DRAM
- What is the difference between a latch and a flip-flop
- What is metastability? How to fix this problem?
- What is a source synchronous clocking scheme?
- Design a circuit to divide an incoming clock by 3
- Why is interconnect not scaling as well as transistors?
- What is clock jitter? source jitter and network jitter?
- Relationship between master clock and generated clock? why do we need generated clocks?
- What is the output of an inverter if the VDD and VSS connections are swapped?
- Write verilog code for a 3:1 MUX
- What is zero-wire-load timing?
- What are various clock tree structures? What are the advantages, disadvantages of clock tree, H-tree, clock mesh?
- What is power gating?
- What is clock gating?
- What is an ICG? How do you model the fan-out of an ICG in synthesis?
- Explain the concept of MCMM (Multi-Corner-Multi-Mode)
- What is leakage power, dynamic power and internal power? How to reduce leakage power, dynamic power and internal power?
- What is elmore delay model? Compute the delay of an RC tree using elmore delay model
- What is power grid? What stage of the design steps is it planned?
- Hierarchical design planning, what complexities get added on when we split a big design into blocks?
- What is a level shifter, retention flop?
- How do you sign-off static IR drop and dynamic IR drop?
- How to minimize addition of hold buffers?
- Write verilog code for a regular encoder and a priority encoder
- What is JTAG?
- What is mBIST?
