- Is NDR better or shielding better for clock tree synthesis?
- Design a circuit which outputs a frequency of 2f with an input of f.
- A, B, C are unsigned 32-bit numbers. How many bits are needed for Y = (A * B) +C?
- Design a Synchronous 2-bit counter using 2 DFFs?
- Write verilog code for a Flip-flop with an asynchronous reset
- How do you declare arrays in perl? Declare an array {3, 2}.
- What are feedthough paths?
- What is noise margin?
- Why should we use inverters on the clock tree to minimize clock cycle distortion?
- Write UPF code for a small design.
- What techniques will you use to mitigate channel congestion?
- What are the advantages and disadvantages of different placement algorithms?
- After base tapeout how do you implement metal only ECOs?
- Design a sequence detector of the pattern 11011.
- Design an XOR gate using only two 2:1 mux.
- Design a FSM for traffic light controller
- Design a johnson counter in verilog.
- Equations for resistance and capacitance of a wire.
- What happens if we increase the number of contacts or via between metal layers (redundant via insertion)?
- Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A &B, which one would you place near the output?
- Explain the operation of a 6-T SRAM cells.
- What is body effect?
- What is latch up? Explain the methods used to prevent it?
- What is resistive shielding?
- Details on FD-SOI technology?
- What are various synthesis optimization techniques?
- What is retiming? How is it used to optimize the design?
- How are standard cells characterized? Example of characterization of a AND gate
- Given a library with several functions, channel lengths, VT-types, how do you prune the cells list for synthesizing the design?
- In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture flop? Why?
- The blocks are timing clean and when integrated at top-level there are lot of setup and hold violations. What are all the possible causes of these new violations?
- What is binning? How do you determine the criterion for CPU binning?
- What is DVFS?
- How do you resolve congestion?
- Explain in detail how clock tree is built by the tool?
- Explain the tool process flow of standard cell placement?
- Explain skew, latency, insertion delay?
- What will be your road map for PnR flow if starting utilisation is 80% and it’s a rectilinear block?
- In how many corners did you close the timing? Write the corner names. Among these which was the hardest corner to close and why?
- Why assign statements are not allowed in netlist? What will happen if we proceed with it?
- Halo is used to protect pins of macro why? Why only for macro?
- Why vss is preferred over vdd for shielding?
- Whether end cap cells will be used for power continuity? If yes why?
- Why spacing between abutted macros is given? Why that spacing is required in fabrication?
- Whether min pulse width violation effect timing or functionality of design? How?
- Whether any factor other than temperature depend on net delay?
- How you go about fixing timing violations for latch- latch paths?
- How will you design inserting voltage island scheme between macro pins crossing core and are at different power wells? What is the optimal resource solution?
- What are various formal verification issues you faced and how did you resolve?
