- What are SDC constraints, how do you decide that a path is a false path?
- What is max transition? How you decide that value?
- How do you set max output load (based on what factors?)
- What are the inputs to Prime Time?
- What do you do for low power design?
- What are retention registers?
- What are HVT cells, how area increases with HVT cells?
- What does CTS do for routing clocks? Global routing?
- How global routing is different from Detailed routing?
- How GR will handle congested paths, what is its impact on delay?
- What is single case, worst case and best case and OCV analysis?
- How can one library have many values for same input slew and output load?
- Will you give constraints for via in CTS or not. How vias will affect the clock routing?
- Do you know about input vector controlled method of leakage reduction?
- Methods of leakage reduction?
- Is increasing power line width and providing more number of straps are the only solution to IR drop?
- If you import a LEF for a macro and you find out that the macro pins are moved from boundary to centre, what will be your approach?
- What if you allow the cell to be placed in the halo region around macro? Can you do that? Why?
- Why metal density rules are important?
- Why power stripes routed in the top metal layers?
- Did you get Antenna problem in your project for all the metal layers? How did you fix them?
- How do you reduce power dissipation using High Vt and Low Vt on your design?
- What are the various statistics available in IR drop reports?
- What is the importance of IR drop analysis?
- What is the difference between ndm generation using oasis and using lef?
- Discuss the steps involved in Layout Versus Schematic?
- Define ERC?
- What are the Signoff checks after generating layout?
- What are the different inputs of extraction tool?
- What are the different types/formats of output of the Extraction Tool or the Parasitic Data?
- What type of information, we can obtain after running the extraction tool?
- For coupling cap and ground cap is there different dielectric constant or it is same? If it is different why?
- In lower technology, coupling capacitance is always a challenge. For reducing the coupling capacitance what techniques we are using right now?
- What is the difference between 40nm & 7nm?
- What is the difference between refine placement & refine opt?
- Can you tapeout the chip with maxtran violation?
- You build clock tree for 500MHz, can we use the same for 400MHz clock without making any changes?
- What is UPF?
- How do hold fixing for reg to out path?
- How do you set uncertainty for interclock domain path?
- What is double patterning?
- What is an ICG? How do you model the fanout of an ICG in synthesis?
- What is pipelining register?
- What is path group? How did you do path group?
- What is useful skew?
- What are the different types of NDR rules you used and how they affect the high frequency and low frequency networks
- What is skew group? What is top, trunk and leaf? What is transition value you give in that?
- How gating checks are done? Which is a better ICG according to you AND based one or OR based one ?
- What are the challenges in placement and how to resolve the congestion at IO pins? Will you report it or you will fix it?
- Will LEC check pass after scan-chain reordering?
