- If you have 10,000 DRC violations on a post-route database, what would be your approach to fix these violations?
- Design AND, OR and NOT gates using Muxes
- How to fix glitch violations?
- What is Multi-Input-Switching (MIS)? How to margin for MIS in timing constraints?
- What is a Transition Delay Fault?
- A chip fails to function when it boots up, however, as the temperature is increased, it starts to operate correctly, what could be the reason for it?
- What are Decap cells? What is the purpose of it?
- How to select SRAM macro cells for design?
- What is a CCS timing model? What deficiencies are addressed from a NLDM timing model?
- Why should we sign-off max_trans and max_cap violations before chip tapeout?
- What is miller cap?
- What is temperature inversion?
- Write a TCL script to find if two rectangles overlap
- What are the differences between moore and mealy models?
- Differences between logically_exclusive, physical_exclusive, asynchronous clock groups
- Clock gating checks
- How do planar transistors and FinFets differ? Which transistors will have more Performance and why?
- What is DIBL effect?
- What is double patterning?
- What are blocking and non-blocking assignments in verilog? Details of both these Statements
- What are various techniques to fix a timing violation?
- State machine to divide the clock by 3/2?
- What is the impact of dummy fill on timing? How does it affect setup and hold timing
- What are the different techniques to mitigate congestion in a design?
- What is cell padding?
- What is congestion driven restructuring?
- Explain the concepts of throughput and latency
- What is cache miss?
- What is pipelining?
- Differences between asynchronous reset and synchronous reset
- What is a reset synchronizer?
- What are various synchronization techniques in clock domain crossings?
- What is Moore's law and Dennard Scaling?
- What is multi-bit flip-flop? What are the advantages, disadvantages using them in Synthesis?
- How to achieve correlation between synthesis and PnR?
- How to achieve correlation between PnR and sign-off timing?
- When you have a path with all combinational gates and it is violating by a big number after synthesis, there is no scope to upsize or vt swap, what will you do?
- What is ECC correction in memories, how is it different from parity? What are the pros and cons of these techniques?
- What are the various techniques to decrease clock skew?
- What is useful skew?
- Write setup and hold timing equations for a T-Flip-Flop
- Difference between array and dictionary in TCL programming language
- How will you fix AC EM violations during chip closure?
- What are stuck-at-faults?
- Design a circuit to generate Fibonacci numbers?
- Design a clock mux for glitch free clock switching?
- Design a XOR gate using NAND gates?
- What is time borrowing when you use latches?
- Can there be negative hold time? Explain a scenario/circuit resulting in negative hold time requirement?
- Can setup requirement time be negative? Explain.
