- How do you calculate maximum frequency given setup, hold, clock and clock skew?
- Consider a timing path crossing from fast clock domain to slow clock domain. How do you design synchronizer circuit without knowing the source clock frequency?
- How to solve cross clock timing path?
- In StarRC, what is un-annotated Nets? Is it ok to proceed with the SPEF that contains un-annotated nets?
- How do you fix setup and hold violations in scan mode?
- What are min-density rules and why do we need them?
- In which scenario (best,typ,worst) you will run power optimization. Justify your answer.
- Explain IR drop analysis and in which scenario (best,typical,worst) will you run IR drop analysis? Justify your answer.
- What is an Isolation cell? What are the types of isolation cell and how you choose which cell to add?
- Which check is frequency independant, setup or hold? Have you heard of frequency dependant hold check?
- What is ERC?
- What is the difference between graph based and path based analysis?
- What are the different physical only cells and why do we need them?
- Say after CTS, your skew target is met but your latency is more than the expected, is it ok to proceed? Justify your answer.
- Did you use clock buffer or clock inverter in your design and why?
- What is a multi cycle path? For a multi cycle path of 4 cycles, on which cycle edge do setup and hold check occur?
- What is the difference between 9T and 12T cells in terms of area, performance and power?
- What is max_fanout constraint? Say your design's timing is fine but you have at least one (or more) max_fanout violation. Is it ok to tape out the design without clearing the max_fanout violation?
- How do you arrive at max_transition constraint value?
- What is max_trans constraint? Say your design's timing is fine but you have at least one (or more) max-tran violation. Is it ok to tape out the design without clearing the max_transition violation?
- A netlist consisting of 500k gates and I have to estimate die area and floorplanning. How do I go about it?
- How to do floorplanning for multi vdd designs?
- How to control via generation when do special route for standard cells, such how to preserve gaps between vias for other net routing?
- What actually happens in power planning? What is the main aim of power planning?
- How power stripes are useful in power planning?
- What are the different ways in which antenna violation can be prevented?
- What is the function of tie-high and tie-low cells?
- What are the changes that are provided to meet design power targets?
- What are the different measures that are required to achieve the design for better yield?
- What are the different classification of the timing control?
- Why not inductance in cmos design?
- What are the input files required to run STA?
- What is the information present in these files which helps for delay calculation?
- What is the different between Crosstalk and without crosstalk based STA analysis.
- In the Hierarchical design, there are different Blocks. How are we capturing the timing information of those blocks in our design?
- What is the difference between PVT corner and RC corners?
- What is the main difference between OCV and AOCV?
- What are the different reasons for high voltage drop in design?
- How to find high IR drop is due to high impedence?
- What is the impact of width variation of a wire on resistance?
- Difference between Vector and Vectorless analysis?
- What is the impact of temperature on resistance?
- In what form package is contributing to IR drop, give formula only for total drop?
- What is the flow for Power and IR drop analysis?
- What are the causes for Static and Dynamic issues?
- Mention solution for Static and Dynamic IR drop issues?
- What is the issue we will see if a wire is current requirement is very high than its capacity?
- What factor causes ESD issues?
- What is the use of switch cells, how those are placed in the design?
- What is the formula for Switching Power?
