- How will you make sure that your power structure is good?
- Why we are following certain guidelines for macros placement and what are those guidelines?
- What is the minimum space required between macros if channel is in non-pin side of macros?
- What is the distance between tap cells in your design?
- How you will perform cell spreading in placement if congestion is there?
- Tell me about 2-pass approach in placement.
- Why we are not taking care about hold violations at placement stage?
- What are differences between OCV and POCV?
- What are the different ways to fix setup and hold? Which one is difficult to fix, setup? Or hold?
- Which violation you will fix first, setup or hold?
- How will you improve your insertion delay?
- What happens if you place macros at the centre?
- If there is a situation that you have to place the macro at the centre then what techniques you employ to reduce the issues like congestion and timing?
- Issues you face in placement stage? and how do you fix them?
- Why will you check setup in placement stage and why will you check hold after cts?
- Placement optimization techniques?
- Write setup and hold equations?
- Techniques to fix setup and hold?
- If you have to optimize the design but still you have setup violations how you will you fix them?
- What is CTS?
- What is Clock tree specification file?
- How do you know the time slack is acceptable to go next stage?
- What does def file consists of?
- What does LEF file consists of?
- What is crosstalk?
- What are NDR rules? Why we want to apply them?
- What is difference between clock buffer and normal buffer?
- Buffer or inverter which one is preferable in CTS?
- What is latency?
- What are the inputs for LVS?
- What is metal pitch?
- What is multi cycle path?
- What is OCV AND AOCV?
- Do you know anything about DPT?
- What are the contents of SDC file?
- If one path have both setup and hold violations? How you will fix that path?
- Do you know about negative and positive skew? Briefly can you tell about that?
- What is the difference between flat and hierarchical cells?
- Which is more complicated when u have a 48 MHz and 500 MHz clock design?
- How do you place macros in a full chip design?
- What parameters (or aspects) differentiate Chip Design and Block level design?
- If the routing congestion exists between two macros, then what will you do?
- If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
- How to calculate core ring width, macro ring width and strap or trunk width?
- How to find number of power pad and IO power pads?
- How the width of metal and number of straps calculated for power and ground?
- What are the problems faced related to timing?
- During power analysis, if you are facing IR drop problem, then how did you avoid?
- Define antenna problem and how did you resolve these problem?
- How delays vary with different PVT conditions? Show the graph.
