- What is static IR drop and dynamic IR drop?
- How to minimize addition of hold buffers?
- Write Verilog code for a regular encoder and a priority encoder.
- What is JTAG?
- What is mBIST?
- If you have 10,000 DRC violations on a post-route database, what would be your approach to fix these violations?
- Design AND, OR and NOT gates using Mux?
- How to fix glitch violations?
- What is Multi-Input-Switching (MIS)?
- How to margin for MIS in timing constraints?
- What is a Transition Delay Fault?
- A chip fails to function when it boots up, however, as the temperature is increased, it
- Starts to operate correctly, what could be the reason for it?
- What are Decap cells? What is the purpose of it?
- How to select SRAM macro cells for design?
- What is a CCS timing model? What deficiencies are addressed from a NLDM timing Model?
- Why should we sign-off max_trans and max_cap violations before chip tape out?
- What is miller cap?
- What is temperature inversion?
- Write a TCL script to find if two rectangles overlap.
- What are the differences between moore and mealy models?
- Differences between logically exclusive, physical exclusive, asynchronous clock groups.
- Whate is Clock gating check?
- What are Setup & hold clock gating checks?
- How do planar transistors and FinFets differ? Which transistors will have more Performance and why?
- What is DIBL effect?
- What is double patterning?
- What are various techniques to fix a timing violation explain with examples.
- What is the impact of dummy fill on timing?
- What are the different techniques to mitigate congestion in a design?
- What is cell padding?
- What is congestion driven restructuring?
- What are various synchronization techniques in clock domain crossings
- How to achieve correlation between PnR and sign-off timing.
- How to achieve correlation between synthesis and PnR.
- When you have a path with all combinational gates and it is violating by a big number after synthesis, there is no scope to upsize or VT swap, what will you do?
- What are the various techniques to decrease clock skew?
- What is useful skew?
- What is time borrowing when you use latches?
- Is NDR better or shielding better for clock tree synthesis?
- The blocks are timing clean and when integrated at top-level there are lot of setup and hold violations. What are all the possible causes of these new violations?
- What is DVFS?
- Which design is more complicated 10MHZ or 100MHz?
- What are the power gating cells?
- What is HFNS (high fan-out net synthesis)?
- What is Electro migration (EM)?
- Why NAND gate is preferred than NOR?
- What is isolation cell?
- What is retention flop?
